Testing system for circuit points that are normally operated in a predetermined sequence

ABSTRACT

A system for monitoring the operation of a circuit configuration including test circuit points therein is disclosed wherein a test network is utilized including a plurality of impedance elements, such as resistors, coupled between the test circuit points and a load impedance element, such as a resistor, with the output from the load impedance element being sensed by, for example, an oscilloscope. The plurality of impedance elements are selected to have a predetermined relationship with respect to each other, such as being weighted for monitoring a counting operation or having substantially equal values for a sequential operation.

United States Patent Inventor Frank Di Nicolantonio [56] References Cited Willhmsville, UNITED STATES PATENTS 3 2'- rz'g z 2,878,450 3/1959 Rabier 324/121 f t 1971 3,398,363 8/l968 Mortley 324/73 Assign w I. 8 Electric Corporation 2,588,209 3/ l 952 Crapuchettes 324/ 140 X Pittsburgh, Pa. Primary Examiner-Alfred E. Smith Attorneys-RH. Henson, C. F. Renz and A. S. Oddi ABSTRACT: A system for monitoring the operation of a cir- TESTING SYSTEM FOR CIRCUIT POINTS THAT cuit configuration including test circuit points therein is dis- ARE NORMALLY OPERATED IN A closed wherein a test network is utilized including a plurality PREDETERMINED SEQUENCE a l s h t l d b t th 12 Chims 7 Damn: as. o rmpe ance e emen suc as resrs ors, coup e e ween e test circuit points and a load impedance element, such as a re- U.S. CI....L 324/73, sistor, with the output from the load impedance element being 324/l40 sensed by, for example, an oscilloscope. The plurality of im- Int. Cl. Gfllr 15/12, pedance elements are selected to have a predetermined rela- 6011' 7/00 tionship with respect to each other, such as being weighted for Field at Search 324/73, monitoring a counting operation or having substantially equal values for a sequential operation.

I'O DI OR SENSIW CIRCUIT TO DISPLAY OR SENSING CIRCUIT RuL PATENIEI] M1831 IIIII SHEET 1 OF 2 '(JWO L L To DISPLAY W 0R SENSING W R cIRcuIT RwLPo PI P2 P4 CO\- 3 1 7 L CLOCK OSCILLATOR FFZ FF4 R 7 P 4 Jw2 Jw4 i i i PJ Pg 34 PL 2; 54 P I PZ 5 Pl Pg 4 I I I NAND NAND NAND NAND NI N2 N3 N4 I INVERTER INVERTER INVERTER INVERTER II I2 [3 14 Jul- Ju2 Ju3 Ju4 I DO Rul DI Ru2 D2 Ru3 D3 Ru4 JuO To DISPLAY 0R SENSING RuL CIRCUIT l r F IG.2.

T0 SEPARATE TEST POINT OUTPUTS OF LOGIC ELEMENTS TO DISPLAY 0R SENSING cIRcuIT WITNESSES- Fronk Di Nicol TTORNEY TESTING SYSTEM FOR CIRCUIT POINTS THAT ARE NORMALLY OPERATED IN A PREDETERMINED SEQUENCE BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to systems for determining the output of various points in a-circuit configuration and, more particularly, to systems for monitoring the operation of the circuit configuration. 2. Discussion of the Prior Art Because of the multiplicity of logic components in digital systems, testing or monitoring the operation of the system and tracking down any malfunction in the system become serious considerations. Each of the logic components is ordinarily checked for operability prior to interconnection into the total system. Also the logic components commonly are tested once interconnected into the system under test conditions, that is, prior to placing the total system in its normal operating mode. The testing of the various components ever under test conditions is a tedious and timeconsuming task and does not of necessity insure that once the system is put into its normal operating mode that proper operation will result.

In a test procedure it is standard practice to select certain test points within a circuit configuration and to check the output of this circuit point to determine whether it is proper for the given test procedure. The common method of doing this is merely to connect the selected test point to an oscilloscope to display the waveform developed at the test point. In this manner the various test points of the system configuration can be checked individually. If a multichannel oscilloscope is utilized, for example, a four-channel oscilloscope, four individual outputs for circuit points could be displayed at one time. However, even using a multichannel oscilloscope, the number of circuit point-outputs that can be observed at a given time is limited; and it is required that these outputs are disconnected so that others may be displayed as thetesting procedure continues. Moreover, such a test procedure again does not insure that once a system is-placed in its normal mode of operation that the system will operate as intended. Monitoring the operation of a digital system once placed in its normal mode of operation is quite difficult due to the limited number of test points that can be observed even with a multichannel oscilloscope, and, moreover, most digital systems are not adapted for testing or monitoring while in operation. If a malfunction should occur in the system operation, it is very difficult to determine which of the logic components is improperly operating or even to isolate the particular logic function which is causing the difficulty. It would thus be highly desirable if the digital system could be monitored when it is in its normal mode of operation, and if a malfunction should occur that the source of the malfunction could be quickly traced for corrective action. Moreover, it would be highly advantageous if the monitoring system required a minimum of additionalcomponents and would permit the display of outputs from a large number of circuit points of the circuit configuration.

SUMMARY OF THE INVENTION Broadly, the present invention provides asystem for monitoring the operation of a circuit configuration wherein a testing network is utilized for monitoring the composite output of a plurality of test circuit points of the circuit configuration, with the composite output being indicative of the operation of the circuit configuration.

BRIEF DESCRIPTION OF THE DRAWING.

FIG. I is a schematic diagram of the testing network as utilized in the present invention;

FIG. 2 is a block diagram of acircuit configuration wherein testing networks of the present invention are incorporated therein;

different modes of operation of the circuit configuration of FIG. 2; and

FIGS. 5A and 5B are display waveform outputs indicative of two different modes of operation of'the circuit configuration of FIG. 2.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, the basic testing network the present I invention is shown. A plurality of impedance elements R1, R2,

R3, RN, which may comprise resistors, have one end commonly connected and the other free ends are to be connected to separate test point outputs of various logic elements of a circuit configuration. At the respective test circuit points either a binary l or O logic output will be developed at a given instant in time. The commonly connected end of the resistors R1, R2, R3, RN define a sensing junction JO. A load impedance element RL, which may comprise a resistor, is connected between the sensing junction JO and a source of operating potential which supplies a direct voltage V. The voltage supply V may comprise a direct voltage of positive or negative polarity of a predetermined magnitude depending upon the connection of the network into a circuit configuration.

Of the plurality of resistors, three are shown in solid lines R1, R2 and R3 and the resistor RN is shown in dotted lines to indicate that any selected number of resistors can be utilized in the plurality with the respective free ends thereof being connected to a designated test circuit point of the circuit configuration.

The resistors R1, R2, R3, RN are selected to have a predetermined relationship with respect to each other and in a weighted type of testing network the resistance values will be weighted, while in other applications termed an unweighted" type of testing network the resistors will all have substantially the same resistance. The load resistor RL may be selected at any convenient value of the particular configuration. The load resistor RL carries the total current applied to the respective plurality of resistors RI, R2, R3, RN, and, in

response to the total current, a composite voltage is developed across the load resistor RL. The composite voltage is sensed at the sensing junction J0 and is applied to a display or sensing circuit which'may ideally comprise a pair of vertical deflection plates of an oscilloscope. For each testing network as shown in FIG. 1, only one channel of the oscilloscope is required for displaying the composite signal appearing across the load resistor RL in response to the individual outputs of the selected test circuit points as applied to the resistors R1, R2, R3, RN.

FIG. 2 shows a circuit configuration employing a plurality of logic components arranged in a predetermined manner to perform a desired logic function. Testing networks of the weighted and unweighted types are incorporated into the circuit configuration of FIG. 2 and are connected to selected test circuit points for monitoring the operation of the circuit configuration. The circuit configuration as shown in FIG. 2 is given herein only by way of example for demonstrating the use of the two types of testing networks, and it should be understood that the testing networks could be incorporated into any circuit configuration utilizing logic components.

The circuit configuration as shown in FIG. 2 is intended to perform the function of generating four separate pulse outputs D0, D1, D2 and D3, which have a predetermined time duration and time sequence as shown in FIG. 3, curves D0, D1, D2 and D3, respectively. The outputs D0, D1, D2 and D3 are generated in response to the output of a clock oscillator CO which is shown as waveform P0 of FIG. 3. The clock output PO is applied to a first bistable flip-flop circuit FFl which supplies in response thereto an output P1, shown in curve P1 of FIG. 3, and also a complementary output PI at a separate out-" clock oscillator CO so that it changes states whenever output PO changes from a 1 logic state to a logic state. For the purposes of explanation, it may be assumed that a l logic state is a positive voltage and a 0 logic state is ground potential.

Thus, as shown in FIG. 3, the output P1 of the flip-flop FF] is at one-half the frequency of the clock output P0. The output P1 of the flip-flop FFI is applied to a second bistable flipflop FF2 which is responsive to change state whenever the output P1 of the flip-flop FF 1 changes from a l to a O logic state. The flip-flop FF2 supplies an output P2 as shown in curve P2 of FIG. 3 and a complementary output P 2. The frequency of the output P2 is at one-half the frequency of the output P1. A third bistable flip-flop FF4 is also provided and received the output P2 and is responsive to the change of the output P2 of the flip-flop FF2 changing from a I to a 0 state. The flip-flop FF4 provides an output P4 as shown in curve P4 of FIG. 3 and a complementary output P4. The frequency of the output P4 is one-half the frequency of the output P2. The output P4 from the flip-flop FF4, if desired, may be supplied to other flip-flop circuits or other logic components if desired. In the present example only three flip-flops FFl, FF2 and FF4 have been shown capable of counting to the number seven before resetting. If higher number counts are desired, of course, additional flip-flop states could be added. In FIG. 3 only the primary outputs P1, P2 and P4 are shown. The complementary outputs P1, P2 and I 4 have not beenshown in that they are the logical inverse of the primary outputs P1, P2 and P4, respectively.

Receiving the gitputs P1, P2 and the complementary outputs P I, P2 and P4 are four NAND logic circuits N1, N2, N3 and N4. The NAND Nl receives Fl, P2 and W, the NAND N2 receives P1, P2 and P], the NAND N3 receives P l, P2 and W, and the NAND N4 receives P1, P2 and P3. The logical operation of each of the NANDs N1, N2, N3 and N4 is such that for a 0 logical output to be supplied therefrom a l logical input must be supplied to each of the inputs. Under all other input conditions the NAND will supply a l logical output therefrom. The output of the NANDs N1, N2, N3 and N4 are respectively applied to the input of inverters ll, I2, I3 and I4, which invert the input applied thereto to supply the logical complement thereof as the outputs D0, D1, D2 and D3.

The generation of the outputs D0, D1, D2 and D3 according to the waveform diagram of FIG. 3 may be seen from the following. During the time period tO-tl the NAND I receives 1 logical input from I 1, I? and W in that P1, P2, and P4 during this time period are at 0 states and therefore provide a 0 output to inverter I1. The NANDs N2, N3 and N4 each having a 0 applied as an input thereto thus apply 1 output to inverters I2, I3 and I4 which inverts them so that the outputs D1, D2 and D3 are at 0 output levels; The inverter Il, however, receiving a 0 input, inverts this to a I input so that the output D0 is at a l logic state between the times t0 and tl. At the time tl, however, the input I to NAND N1 reverts to a O in that the output changes to a l, which is inverted to a 0 as the output D0. The NAND N2, however, receives three 1 inputs and therefore outputs a 0 to inverter I2 which then supplies a 1 output as the output DI. DI remains at the I output level until the time t2 when Pl goes to 0 and P2 goes to a l. The NAND N3 then outputs a 0 which is inverted to supply the 1 output at D2 during the time period t2-t3. At the time t3, the outputs Pl and P2 are l's and the output P4 is a 0. This causes the NAND N4 to output a 0 which is inverted in the inverter 14 to provide the output D3 at a I level during the time period t3-t4. At the time t4, P4 is a l and P1 and P2 are 0's. P4 is applied to each of the NANDs N1, N2, N3 and N4 therefore each of these will receive a 0 input during the time period t4-t5 and thus the outputs D0, D1, D2 and D3 will be 0 during this time period.

It will thus be seen that the circuit configuration of FIG. 2 provides the output waveforms D0, D1, D2 and D3 as shown in FIG. 3 which may be utilized for any timing or control func- 1 tion as desired. Also the pulse waveforms PO, PI, P2, P4, Pl, P2, N can also be utilized for various logical functions, as desired.

V In the circuit configuration of FIG. 2, test networks of the weighted type and the unweighted type are utilized and receive their inputs from selected test circuit points to provide a composite output for monitoring the operation of the circuit configuration. The three flip-flops FF 1, F F2 and F F4 tandemly connected as shown operate as a counter which counts in a binary fashion. The first pulse X1 from the clock oscillator 60 in the pulse train PO to be counted as shown in curve P0 of FIG. 3 has a 0 value during a time period beginning at t]. Subsequent pulses to be counted are indicated as X2, X3, X4, X5, X6 and X7. The counting operation for the flip-flops FFI, FF2 and FF4 is summarized in the following table.

TABLE A Pulse Outputs No. P1 P2 P4 X0 0 0 O XI l 0 0 X2 0 l 0 X3 1 l 0 X4 0 O 1 X5 1 O l X6 0 l 1 X7 1 l l Whenthe flip-flop FFI receives the eighth pulse X8, all of the flip-flops will have a zero primary output P1, P2 and P4 thereby resetting the counting operation.

The respective outputs PI, P2 and P4 and the complementary outputs P1, P2 and W of the three flip-flops are thus interrelated. Due to this fact, it is not necessary that each of the outputs be individually displayed in order to determine whether the counting operation is taking place as desired. Whenever the outputs in a particular logic operation are interrelated, for example, in a binary counting scheme, it is highly desirable to utilize a weighted type of testing network. In FIG. 2, components of the weighted testing network are designed with a which are weighted according to the number designation, that is, the resistance of the resistor Rw/2 is equal to one-half the resistance of resistor Rw and the resistor Rw/4 is equal to onefourth the resistance of the resistor Rw. The bottom end of the resistor Rw is connected to the test circuit point .lwl at the complementary output PT of the flip-flop FF 1, the bottom end of the resistor Rw/2 is connected to a test circuit point .lw2 at the complementary output P2 of the flip-flop FF2 and the bottom end of the resistor Rw/4 is connected to the test circuit point Jw4 at the complementary output P 4 of the flip-flop FF4. The top ends of the resistors Rw, Rw/2 and Rw/4 are commonly connected to a sensing junction JwO. A load resistor RwL is connected between the sensing junction Jwl and a source of operating potential V+, which in the present example would comprise a positive polarity voltage. The composite voltage developed across the resistor RwL, between the point .lw0 and the V+ terminal, in response to the current supplying through each of the resistors Rw, Rw/2 and Rw/4 is supplied to display or sensing circuit, for example, a pair of vertical reflection plates of an oscilloscope.

The circuit points Jwl, .Iw2 and Jw4 at the complementary outputs of the flip-flops FF 1, FF2 and FF4, respectively, were selected as a matter of convenience and it should be noted that the outputs P1, P2 and P4 could have been selected.

The weighted testing network is so arranged that current will be translated through the weighted resistors Rw, Rw/2 and Rw/4 whenever the complementary output to which the free end of resistors is connected is at a0 binary state. Thus a current path will be provided from the source V+, the load resistor RwL and the respective weighted Rw, Rw/2 or Rw/4. Since the resistors Rw, Rw/2 and Rw/4 are weighted as described and assuming the voltage V+ will cause one unit of w and includes the resistors Rw, Rw/2 and Rw/4 current'to flow in the resistor Rw when Fiis at a zero value, the resistor Rw/2 and the resistor Riv/4 willthen, respectively, permit 2 units of current and 4 units of current to pass therethrough when their respective test points Jw2 and .lw4 are at values. The composite current that passes through the resistors Rw, Rw/Z and Rw/4 passes through theload resistor RwL so that the total voltage VwL developed across the load resistor RwL is the sum of the individual currents through the weighted resistors Rw, Rw/Z and Rw/4times' the resistance value of theload resistor RwL. r

The composite voltage developed across the load resistor RwL for the various complementary outputs F1, F2; and 1 are illustrated in the following Table B.

It can thus be seen from this table thatthe voltage developed by the load resistor RwL increases proportionately as the pulse count from the clock oscillator CO for the pulses'X 1', X3 X3.... As an example of this, for the first pulse X1 1, curve P0 of FIG; 3, one unit voltage Vwl; will be developedby. the load resistorRwl. since only the resistor Rw will pass aunit ofcur rent thereto. This may be seen in that the complementary output fi is at a 0 state permitting the translation of current through resistor Rw, while the complementary outputs F2 and Rare at 1 states which block passageof current through the resistors Rw/2 and Rw/4. In the case when the second pulse XZappears, as shownin Table B, the complementary output. F2 is at a 0 state while the complementary. outputs PT and I7:

are at 1 states. Thus only theiresistor Rw/2.will translate cur rent therethrough which will bezofa magnitude twice that of the current translated by the resistor Rw since. the resistance of the resistor Rw/Z is one-half the value of. the resistor Rw. Hence the voltage 2VwL will be developed across the load resistor RwL due. ,to the doubling of the current flow therethrougl'LFor the third pulse X3-thecomplementary outputs I 1 and P2 are at O and the complementary output P4is a I value. Thus current willbe translated through the resistors Rw and Rw/2. This will mean a current. flow. of one unit throughthe resistor Rw and two units through-theresistor Rw/Z making a total current flowof three units through the load resistor RvvL. Therefore, in response to theflow-of three units of current, a voltage of 3 VwL willbedeveloped across the load resistor .RwL. The operation of the weightedtesting;

flow through the various resistorsof the .testingnetworkwhena] state exists rather than when a 0 state exists this could be I played on theoscilloscopeby con'necting the junction lntland It can be seen from FIG. 4A that the waveform increases in a set manner for each of pulses X1, X2, X3 until th voltage 7VwL is reached within the seventh pulse X7. The then goes to a reference value with the eighth" pul waveform shown in FIG. 4A is for normal operation and any deviation from this normal waveform will be indicative of a malfunction of the counting operation of the flip-flops F Fl, F F2, or FF4.

FIG. 4B shows a malfunction condition wherein'the flip-flop FF4 is not operating properly. Thus as shown in FIG. 4B, the first three pulsescause thestep waveform to be developed as under normal operation. However, when the fourth pulse is received, which would normally cause the complementary output to go to a 0 binary level and cause four units of current to pass through the resistor Rw/4, and also the load resistor RwL, a malfunction of the flip-flop FF4 prohibits this change from taking place. Hence, at this time of the fourth pulse, the voltage developed across the load resistor RwL is zero since there is no current flow through the resistor Rw/4 or the resistors Rw and Rw/2. At the receipt of the fifth pulse, the flipflop EFI causes a 0 complementary output FT to appear which causes oneunit' of current to pass through the load resistor RwLand the resistor Rw with one unit of composite voltage being displayed in FIG. 4BThe sixth and seventh pulses cause the step waveform to rebuild, however, with the absence of the four units of voltage normally developed by the proper operation of the flip-flop FF4.

With the display of the waveform of FIG. 43', it would become apparent to a monitor of the system that the flip-flop FF4. is not functioningproperly and remedial actioncould then betaken to replace or repair this particular logic component. It can thus be seen from the above explanation that the weighted .testingnetwork not only indicates'that a malfunction has occurred in the counting operation but points out which of the. particular logic components of the counter has malfunctioned which expedites. taking corrective action. Only three resistors are shown in the weighted testing network associated with the three flip-flops FFI, FF2 and FF4; It should be understood, of course, that for higher count counters additional resistors weighted according to the ratio: Rw/2", where n is the number of the resistor in the network with the first' resistor Rw having the number 1, could be utilized. Also the weightedtesting network could be utilized in other counting schemes such as a binary coded decimal scheme wherein the'counter resets upon the l0thpulse rather than upon other number counts. Also the. weighted testing network could be utilized in any logic configuration wherein the outputs of the plurality of interconnected logic components have a predetermined relationship with respect to each other, that is, where the respective outputs thereof change in a predetermined pattern in response to the inputs thereto. J

In FIG 2. an unweighted testing network is also incorporated therein for monitoring the operation oftheDO, D1,

DZand D3 outputs of theinverters I}, I2, 13 and I4, respectively. Test circuit points .lul, M2, .1143 and Ju4 are connected 1 respectively at the output of the inverters I1; I2, 13 and I4. Unweighted resistors Rul, Ru2, R143 and" R144 are connected between the respective test points Jul, Ji42,.Iu 3-andJu4 and a accomplished by replacing the positive operating voltage. V+

with a negative operating voltage V- of suitable magnitude to permit current-flow only when ,a selected logicelement hasa 1 output and to block current flow if a 0 output exists.

FIG. 4A shows a display waveform of the normal operation. 7

sensing. junction Ju0. The'unweighted resistors Rid, Ru2, Ru3 and Ru4-may conveniently have the same resistance value. Between the sensing junction .Iu0 and'a source of operating potential V+ isconnected a load resistor RuL, with the volt age developed across the load resistor R'uL being sensedto be applied to a display or sensing circuit such as to vertical deflection plates of an oscilloscope. The source voltage V+ is selected to have a positive polarity.

The outputs D0, D1, D2 and D3 are shown in curves D0, D1, D2 and D3 of HG. 3 and it can be seen that during the time period t-t4 a logical 1 output is sequentially provided under normal operating conditions from D0 through D3. Thus, when one of the outputs D0, D1, D2 or D3 is at a I level, the other three of the outputs are at a 0 level. Thus, with three of the outputs at a 0 level and one at a 1 level, current will be translated from the source V+ through the load resistor RuL and three of the unweighted resistors to develop a three-unit load voltage across the load resistor RuL. No current will be translated through the other resistors in that the output applied thereto will be at a 1 level. As the outputs D0, D1, D2 and D3 sequentially switch from a 1 output at D0 to l outputs at D1, D2 and D3, the voltage across the load resistor RuL will remain substantially constant in that at any given time three of the unweighted resistors will translate current thereto while the other one will be nonconductive.

FIG. A is a display waveform of the voltage developed between the sensing junction point Jul and a ground reference point under normal operating conditions. The display waveform could be conveniently displayed on an oscilloscope by the application thereof to a pair of vertical deflection plates with a suitable time reference being applied to the horizontal deflection plates thereof. As can be seen by FIG. 5A, the constant output voltage is indicated by a straight line disposed a distance of three units, for example, from a ground reference line indicated by the dotted line. As long as the inverters l1, l2, l3 and [4 provide the sequential waveforms shown in curves D0, D1, D2 and D3 of FIG. 3, the substantially constant output as shown in FIG. 5A will be provided. If a malfunction of any of the inverters 11, 12,13 or [4 or of any of the NAND circuits N1, N2, N3 and N4 should occur, the waveform of FIG. 5A will deviate from that shown and would indicate that a malfunction of one of the circuit components has occurred.

FIG. 5B shows a malfunction condition with the display voltage deviating from its substantially constant value during the time interval 2-13 of FIG. 3. The malfunction indicated by the waveform of HG. 5B is that at the time [2 the output D1 has not changed from a 0 to a I level but rather has remained at the 0 level. Therefore, all four of the resistors Rul, Ru2, Ru3 and Ru4 will translate current therethrough so that a four-unit load voltage would be developed across the load resistor RuL. The waveform of HG. 58 indicates that a malfunction has occurred either in the inverter [3 or the NAND N3 which supplies the input to the inverter [3. These two logic elements should be checked in order to correct the malfunction. Any waveform displayed other than the waveform of HG. 5A would be indicative of some malfunction in the circuit configuration requiring corrective action. I

Only four resistors Rul, Ru2, Ru3 and R144 have been shown in the present example, however, it should be understood that other resistors could be utilized. Also, if desired, the test points Jul, Ju2, Ju3 and .lu4 could be taken from the output ofthe NAND circuits N1, N2, N3 and N4. However, by placing test points at the output of the inverters l1, l2, l3 and I4, respectively, malfunctions of both the associated NAND and inverter circuit can be done with a single test point.

It can thus be seen that by the incorporation of the weighted and unweighted testing network into the circuit configuration of FIG. 2 complete monitoring of circuit configuration is provided while the system is operating under normal conditions. lf a malfunction should occur in a logic element thereof, the displayed waveform indicates not only that a malfunction has occurred but also which of the logic components is the probable cause of the malfunction. Moreover, the composite output provided at the weighted sensingjunction Jw0 and unweighted sensing junction Ju0 could be displayed on separate channels of a multichannel oscilloscope and thereby provide complete monitoring of the total system, while state of the art test procedures would require seven separate channels in order to display the separate output information appearing at each of the test circuit points Jwl Jw2, .lw4, Jul, Ju2, Ju3 and Ju4l Although the present invention has been described with a certain degree of particularity, it should be understood that the present disclosure has been made only by way of example and the numerous changes in the details of the circuitry and the construction and the combination arrangement of parts, elements and components can be resorted to without departing from the spirit and scope of the present invention.

What l claim is:

l. The combination comprising:

a. a plurality of logic elements disposed in predetermined manner to perform a selected logic function, each logic element having an output indicative of the logic state of the element,

. a plurality of circuit points each connected to sample the output of a different one of said logic elements, said plurality of circuit points being normally pulsed in a predetermined sequence by their respective associated logic elements,

c. a point of reference potential;

d. a junction;

e. a load impedance connected between said reference point and said junction over the time of said sequence,

f. a plurality of impedance elements, each connected between said junction and a different one of said plurality of circuit points over the time of said sequence, whereby said load impedance senses the composite output of said circuit points; and

g. means connected to said load impedance for sensing the output across said load impedance developed in response to the composite output of said plurality of circuit points, said output of said load impedance being indicative of whether or not the selected logic function is being performed.

2. The combination of claim 1 wherein:

said plurality of impedance elements bear a predetermined relationship to each other.

3. The combination of claim 2 wherein:

said predetermined relationship being that said plurality of impedance elements have respectively weighted im pedances.

4. The combination of claim 1 wherein:

said predetermined relationship being that said plurality of impedance elements have substantially the same impedance.

5. The combination of claim 1 wherein said means for sensing in clause g comprises time referenced visual display means.

6. The combination as in claim 1 wherein each of said plurality of impedance elements is weighted according to the ratio R/2'", where n is the sequence number of the impedance and R is the impedance value of the first in sequence impedance element of the plurality.

7. The combination as in claim 1 wherein said plurality of impedance elements have respectively different impedances weighted in accordance with a desired pattern.

8. The combination as in claim 1 wherein said means for sensing in clause g is connected directly to said junction.

9. The combination as in claim 8 wherein said plurality of impedance elements have substantially the same impedance.

10. The combination as in claim 8 wherein said plurality of impedance elements have respectively different impedances weighted in accordance with a desired pattern.

11. The combination as in claim 8 wherein each of said plurality of impedance elements is weighted according to the ratio R/2"", where n is the sequence number of the impedance and R is the impedance value of the first in sequence impedance element of the plurality.

12. The combination of claim 8 wherein said means for sensing in clause g comprises time referenced visual display means. 

1. The combination comprising: a. a plurality of logic elements disposed in a predetermined manner to perform a selected logic function, each logic element having an output indicative of the logic state of the element, b. a plurality of circuit points each connected to sample the output of a different one of said logic elements, said plurality of circuit points being normally pulsed in a predetermined sequence by their respective associated logic elements, c. a point of reference potential; d. a junction; e. a load impedance connected between said reference point and said junction over the time of said sequence, f. a plurality of impedance elements, each connected between said junction and a different one of said plurality of circuit points over the time of said sequence, whereby said load impedance senses the composite output of said circuit points; and g. means connected to said load impedance for sensing the output across said load impedance developed in response to the composite output of said plurality of circuit points, said output of said load impedance being indicative of whether or not the selected logic function is being performed.
 2. The combination of claim 1 wherein: said plurality of impedance elements bear a predetermined relationship to each other.
 3. The combination of claim 2 wherein: said predetermined relationship being that said plurality of impedance elements have respectively weighted impedances.
 4. The combination of claim 1 wherein: said predetermined relationship being that said plurality of impedance elements have substantially the same impedance.
 5. The combination of claim 1 wherein said means for sensing in clause g comprises time referenced visual display means.
 6. The combination as in claim 1 wherein each of said plurality of impedance elements is weighted according to the ratio R/2n 1, where n is the sequence number of the impedance and R is the impedance value of the first in sequence impedance element of the plurality.
 7. The combination as in claim 1 wherein said plurality of impedance elements have respectively different impedances weighted in accordance with a desired pattern.
 8. The combination as in claim 1 wherein said means for sensing in clause g is connected directly to said junction.
 9. The combination as in claim 8 wherein said plurality of impedance elements have substantially the same impedance.
 10. The combination as in claim 8 wherein said plurality of impedance elements have respectively different impedances weighted in accordance with a desired pattern.
 11. The combination as in claim 8 wherein each of said plurality of impedance elements is weighted according to the ratio R/2n 1, where n is the sequence number of the impedance and R is the impedance value of the first in sequence impedance element of the plurality.
 12. The combination of claim 8 wherein said means for sensing in clause g comprises time referenced visual display means. 